The boost converter comprises a bridge rectifier having the ac power line at its input (Vin is its rms value); a capacitor Cin, which serves as a high-frequency Smoothing filter, connected across the output terminals of a bridge with the negative terminal connected to ground; an inductor L with one end connected to the positive terminal of Cin . a power Switch (typically a MOSFET) M having the drain terminal tied to the other end of the inductor L, the Source terminal to ground via a resistor RS that allows sensing the current flowing through M (i.e., the current flowing through L when M is ON) as a positive voltage drop across RS itself .a diode D having the anode tied to the node common to L and MOSFET’s drain and the cathode connected to the positive plate of the capacitor Co that has its negative plate connected to ground GND. This boost converter generates at its output terminals across Co a dc Voltage Vo that will supply the load, typically represented by a dc-dc converter, in other cases, electronic lamp ballast or a motor.
Here we are concentrating topology based on the concept of pulse-width modulation (PWM) currently in use in PFC pre-regulators: used when the boost converter is operated at fixed frequency with continuous conduction mode (CCM) current of the boost inductor, forces the average boost inductor’s current to follow a sinusoidal reference;
•Considerations during the design:
Too much energy stored in the Llk (or external inductance), produce an increment in the conduction losses in every component through a circulating current . For the magnetizing current, the effect is the same. The ideal design will have low magnetizing current, and the leakage inductance integrated in the operation for achieving ZVS without additional inductances.
General Structures of Power Converter Code
General Structures of Power Converter Code
dsPIC® consists of a number of different functional blocks:
- Intelligent Power Peripheral (IPP): ADC
- Intelligent Power Peripheral (IPP): PWM
- Intelligent Power Peripheral (IPP): Comparator
- DSP core
- Other peripherals
In order for these blocks to work together to perform the desired tasks, a set of commands (instructions) have to be supplied to the dsPIC® DSC which will execute them.
Instruction Set Architecture Overview
The following shows an example of the program flow of three sets of instructions: initialization, main, and ADC interrupt.
Interrupt
The following shows how the two interrupts stop the sequential execution of the commands (instructions) and force the system to execute in response to the specific event that has generated the interrupt by the called Interrupt Service Routine (ISR).
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Soft Start, Sequencing
Soft Start, Sequencing
The control of Switch Mode Power Supplies (SMPS) has traditionally been done in the analog domain. Thanks to the high performance of Microchip’s Digital Signal Controller (dsPIC® DSCs), many auxiliary functions such as Soft Start and Power Sequencing can be embedded into the dsPIC DSC in the digital domain. In this section, we’ll focus on the operation and implementation of these two special functions.
Note:
Soft start and power sequencing can be implemented in the Level 2 Integration Level.
Soft Start
When a power conversion system first starts up, the various passive components, such as capacitors and inductors, are completely depleted. In that situation, a sudden rise in the supply voltage can cause large voltage and current spikes in the system. Therefore, it’s important to have a soft start mechanism implemented in all stages of the power supply to ensure that system components do not undergo unnecessary stress. As a result, many modern high performance applications require special care in designing the power conversion applications. Two recurring requirements are the ability to freely select the slope of the voltage being supplied to the system devices (soft start) and the ability to turn on (and off) the devices in a pre-selected sequence (power sequencing).
Soft start provides these basic features:
- When the system is switched on, the output voltage should rise from zero to the final value (ramp up) following a smooth ramp.
- When the system is switched off, the output voltage should fall from the initial value to zero (ramp down or decay) following a smooth ramp.
When the system is switched on, the output voltage must ramp up from zero to the steady state value smoothly. This is because it reduces the inrush current, which could damage the components, and reduce the overshoot and oscillations that may otherwise be generated. The same mechanism should also be applied from the steady state voltage to zero (decay) when switching off the unit.
In analog designs of power conversion systems, soft start is done mainly by using external resistors and capacitors, although many analog controllers provide a built-in soft-start feature. Analog controllers, however, provide limited flexibility in choosing the soft start time duration and startup delay. While it’s possible, the implementation of delays and sequencing is implemented by specialized devices, which add costs and system complexity. In analog soft start implementations, there are normally two different approaches. Either the PWM chip has a preset ramp duration or it can be set using external resistors and capacitors.
The disadvantages of analog soft start are:
- Lack of versatility if the ramp duration is set by the external analog controllers.
- The ramp duration varies according to the components’ tolerances, temperature, and humidity specifications.
In the dsPIC® DSC, soft start can be easily implemented using a soft start routine for each stage of the power supply, each with a configurable duration (ramp up or down) and delay by using a digital power supply implementation, eliminating the shortcomings of analog implementations. For each output voltage, the corresponding reference voltage (Vref) is driven by the system in order to follow the desired ramp. The desired voltage ramp can then be generated by the soft start routine in the dsPIC DSC.
An example of a soft start routine is shown below.
void PFCSoftStartRoutine()
{
Delay_ms(STARTUP_DELAY)
pfcVoltagePID.controlReference = pfcInitialOutputVoltage;
while (pfcVoltagePID.controlReference <= PFCVOLTAGE_REFERENCE)
{
Delay_ms(SOFTSTART_INCREMENT_DELAY);
pfcVoltagePID.controlReference += PFC_SOFTSTART_INCREMENT;
}
pfcVoltagePID.controlReference = PFCVOLTAGE_REFERENCE;
}
The soft start routine is called immediately after initialization of the dsPIC® DSC. A startup delay is first called, and then the output voltage reference is set to the measured output voltage. The reference is then incremented by a fixed amount until the final desired reference is reached. At this point, the soft start routine ends and normal system operation begins. The digital controller (DSC) allows for very flexible use of this soft start routine. The same routine can be called with different parameters at different times. For example, if the system is attempting to restart after a fault has occurred, the startup delay and soft start duration can be modified to a different value adding flexibility and versatility to your power conversion design.
Sequencing
In multi-stage power supplies, there is also a need for sequencing the outputs in a predefined manner, as some outputs are dependent on others. This can be accomplished using a separate sequencing chip, or by using the housekeeping MCU with additional circuitry. A digital power supply eliminates the need for additional hardware because all sequencing and soft start routines can be implemented as part of the power supply control software.
In complex power conversion systems, such as multi-stage power supplies, you may have a number of different chips (controllers, FPGAs, memories, and so on) that require different voltage levels and a specific, well defined sequence of turning-on (and off). In other words, different chips in the system may require more than one supply voltage (VDD) causing power sequencing issues. See figure below. This means that a specific order must be followed (for instance first the MCU, then the FPGA, followed by the rest of the circuits). Predefined ramp up and ramp down duration are often defined by chip manufacturers and must be generated accordingly. In many cases, it is required that these voltages ramp from zero to the nominal output voltage (and vice-versa at switch off) in the correct order and with predefined ramp durations.
Due to the needs of controlling multiple outputs in some power conversion designs. the dsPIC® DSC can cope with all these required functionalities while at the same time taking care of the soft start, power sequencing, over-current, over-voltage protection, and communication.
Sequencing can be implemented in a number of flexible configurations without any additional circuitry. Sequential and ratiometric sequencing schemes are shown below.
A digital power supply offers great flexibility in picking and choosing the soft start and sequencing schemes without the addition of dedicated chips or complex circuitry. In digital power sequencing, if one converter is dependent on the output of another stage, the software can set flags to indicate when one converter is completely turned on, and that the voltage is ready for the next stage to begin ramping up.
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